Job Description

Senior Design Verification Engineer
Must be a US Citizen
Minneapolis, Minnesota (onsite/hybrid)
Full-Time + Health Benefits + 401K Plan with profit sharing + PTO + Stock Option Plan:
An experienced ASIC Design Verification Engineer takes ownership of the full chip development from architecture definition through to release to production. The right candidate will be someone with high aptitude who is currently hands on designing complex digital blocks, with strong knowledge/experience across the complete ASIC/SOC design flow. An ideal candidate will additionally have experience with radiation-hardened design, analog/mixed-signal design and EDA, and std-cell library development.The candidate is expected to design and verify circuits, logic, systems, and algorithms to meet product requirements. The individual will determine the proper method and procedures to be used in the digital system development and determine the best method for verifying the digital system before the complete design is committed to silicon. Candidate must have experience in implementing the proposed method and procedure to design and verify ASIC digital circuits.Additional duties include the evaluation of customer requirements and estimates of effort/expenses for potential new business, and participation in identifying problems with and improvements to, internal design methodologies.Essential Duties and Qualifications:

• Reviewing and editing target specifications as required for completeness and feasibility.
• Developing architectures and specifications for complex design blocks and SOCs.
• Implementing complex digital designs using reusable RTL methods (Verilog, VHDL, SystemVerilog).
• Complex computational architectures and algorithms, such as multi-rate/DSP and xc2xb5P design.
• Modern verification methods, including directed/constrained-random stimuli, assertions, TLM and UVM.
• Collaborative creation of comprehensive verification plans and coverage metrics.
• Multi-supply-domain and UPF methods.
• Constraining and synthesizing digital designs to target cell libraries.
• Static timing, power, and SI analyses of complex digital designs.
• Supporting place & route efforts, including P/G and floorplanning, timing and physical constraints, gated CTS, MCMM setups, back-annotation, timing closure, equivalence checking.
• Planning, implementing, and analyzing designs for DFT, test hooks, and scan/ATPG/JTAG/BIST, and supporting production test with ATE patterns (ATPG and functional) and timeset definitions.
• Proficiency with Synopsys EDA tools (DC-Topo, VCS-MX, PrimeTime, Formality, TetraMAX)
• Proficiency with Mentor EDA tools (Questa, ADMS, Tessent)
• Modern revision-control tools and best-practices in a collaborative, multi-site design community.
• Proficiency with UNIX/Linux including shell scripting, text utilities (e.g., sed, awk, grep), using Modules, high-level programming such as C/C++, PERL/Python/TCL scripting.
• Proficiency with Windows apps, including Word, Excel, PowerPoint, Visio, Project, PDF conversion.

• BSEE/MSEE or equivalent.
• 7+ years of direct industry experience with ASIC and/or SoC design.
• A strong background in RTL based digital IC design using Verilog/SystemVerilog.
• Proven track record of first-pass successes.
• A self-starter with the ability to assume leadership roles.
• Ability to work well in a diverse team environment.
• Willingness to mentor junior engineers.
• Experience with industry standard development tools and methodologies.

Chelsea Search Group